01How Computers Work (online)

Lesson 10.05 · Programs on a tiny CPU

Reading a timing trace

How do you debug a program without guessing?

Beginner friendly · Read → inspect → predict → verify

The question

Do not memorize the diagram immediately. First decide what each arrow must mean. How do you debug a program without guessing?

Record register, bus, PC, control state and memory values after important steps. This is the small idea we need before we can build anything more complicated.

Suppose you have no specialized computer vocabulary yet. Rather than naming a part and demanding that you remember it, define its job. What information exists at the input? What outcome must be produced? Can we state the rule so precisely that a circuit could carry it out?

That is our starting point here. The question is not how to memorize the diagram. It is why this part has to exist and exactly which problem its presence solves.

A picture you already understand

A flight recorder preserves what happened at each checkpoint, not merely the final destination.

Use the analogy only as an entry point. A physical circuit does not need imagination, awareness, or a little operator inside. It needs an arrangement of connections that reacts predictably to the values presented.

Whenever the analogy becomes misleading, come back to the stricter engineering rule: Record register, bus, PC, control state and memory values after important steps.

Notice what we have deliberately not assumed: an operating system, a programming language, or a modern laptop. We are still establishing one small behavior that later components can depend upon.

Build the idea

Our unit of reasoning is the running program. For this kind of system, pay attention to PC, instruction, ACC, flags and side effects. These are the things you can observe or write in a trace table.

For LOAD 4, observe PC fetch, IR load, effective memory address and accumulator update.

That explanation is the mechanism, not merely a metaphor. You should be able to point to an input, explain what rule is applied, and determine exactly which state or output changes.

Plain-English definition

Reading a timing trace

Record register, bus, PC, control state and memory values after important steps.

Useful test: Trace each iteration and verify an explicit termination condition.

Why it is designed this way

The immediate requirement is simple: the rule must be repeatable. Given the same relevant inputs and the same previous state, a deterministic implementation should produce the same defined result. That makes the block useful as a building material.

The next requirement is composition. A later component should not need to understand every internal detail. It should rely on the outputs and timing contract provided by this component.

Code becomes meaningful when successive instructions produce a reproducible trace.

Walk a value through the machine

A diagram becomes much easier when we trace a specific case rather than a vague general statement. Here is a concrete example to hold in your mind:

Worked mental example

For LOAD 4, observe PC fetch, IR load, effective memory address and accumulator update.

  1. Identify the input or starting state. Name the signal, number, address, or instruction involved. Where did it come from?
  2. State the rule precisely. Do not say “the computer knows”; say which selection, comparison, arithmetic step, storage event, or interpretation must occur.
  3. Follow the transformation. For LOAD 4, observe PC fetch, IR load, effective memory address and accumulator update.
  4. Find the destination. Does a register capture a value? Does a gate merely present an output? Does an address select stored data? Keep these actions separate.
  5. Verify against the intended behavior. Trace each iteration and verify an explicit termination condition.

A reliable trace always distinguishes the value being handled from the place carrying or storing it. This will become increasingly important when an address, an instruction, and ordinary data are all represented by patterns of bits.

Read the diagram

Think of each box as a behavior with a defined responsibility. Arrows show the intended flow of data, control, or state changes. The diagram is a simplified logical picture rather than a literal photograph of silicon layout.

Instruction cycle, diagram of connected labeled components
Instruction cycle. Follow the arrows to identify where information travels and what each block contributes.

Reading exercise: Point to the first block and explain what value it can provide. Follow an outgoing arrow. Ask whether the next block transforms the value, chooses among values, or stores the value. Repeat until you reach an observable result.

For a stateful path, remember that a feedback arrow means the future may depend on an earlier output. For an arithmetic path, remember that each bit can have a place value. For control, remember that a command is only useful when it drives concrete enables and selectors.

What this does not mean

A tempting wrong assumption

A final correct output does not prove every intermediate timing or state transition was correct.

This is worth checking because beginners often jump from a correct simple example to an overly broad rule. The simple model is deliberately limited. It should remain precise inside those limits.

To see the boundary, ask: what is the bit width, which signal is interpreted as control, and whether we are talking about an instantaneous combinational output or a stored state? Those details prevent a surprising number of errors.

Real hardware also has nonzero propagation delay, physical limits and implementation choices. Our abstract diagrams ignore these details only where they are not necessary to explain the behavior.

Explain it back

Imagine explaining this topic to someone who has never opened a computer. Your explanation should fit in a few sentences, yet it should not hide the actual mechanism behind words like “magic” or “automatically”.

Start with Record register, bus, PC, control state and memory values after important steps. Then use the concrete case: For LOAD 4, observe PC fetch, IR load, effective memory address and accumulator update.

Finish with the limitation: A final correct output does not prove every intermediate timing or state transition was correct.

That three-part explanation — idea, mechanism, limitation — shows much deeper understanding than simply remembering an acronym.

Try it yourself

Checkpoint

Make a six-column trace for ADD and one conditional branch.

Write down the expected result or sketch the signal flow before revealing the guidance. If you cannot do it without rereading, that is useful feedback about what to revisit.

Reveal the reasoning method

Begin from the exact starting input or stored state. Identify PC, instruction, ACC, flags and side effects. Apply only the transformation described in this lesson: For LOAD 4, observe PC fetch, IR load, effective memory address and accumulator update. Then validate your outcome. Trace each iteration and verify an explicit termination condition.

The key is not how quickly you answer. It is whether each arrow or state transition in your answer has a clear reason.

You can return to Part 10 overview or open an interactive laboratory (online) to test related hardware ideas.