Translate unfamiliar words into actual behavior
The plain-language glossary
136 precise, beginner-readable definitions. This is a dictionary you can return to when a term appears in an instruction trace or architecture diagram.
Accumulator
A register that frequently holds an ALU input and output in a simple CPU.
Address bus
Signal lines carrying the address of a selected memory or device location.
Address space
The range and meaning of addresses accessible to a processor or program.
ALU
Arithmetic logic unit; circuitry selecting between arithmetic and bitwise operations.
AND
A Boolean operation that returns one only when all inputs are one.
ARM
A family of instruction set architectures and CPU designs widely used in many devices.
ARMv6
A version of the ARM architecture supported by the ARM1176JZF-S family.
Assembler
A program converting assembly mnemonics and operands to encoded machine instructions.
Assembly
A readable language closely related to an ISA’s machine instructions.
Binary
A base-two positional number representation using 0 and 1.
Bit
One binary distinction: 0 or 1, represented physically by a distinguishable state.
Bitwise operation
An operation that applies a logic rule independently to corresponding bits.
Boolean algebra
Mathematics of true/false relationships, including AND, OR and NOT.
Boolean expression
A formula built from true/false variables and logical operators.
Borrow
The corresponding concept in direct subtraction; many ALUs report no-borrow instead.
Branch
An instruction that conditionally or unconditionally selects a new control-flow target.
Bus contention
An electrical conflict when multiple active drivers attempt incompatible values on one shared connection.
Byte
A group of eight bits; it has 256 possible patterns.
Cache
Small, relatively fast storage for copies of likely-needed data or instructions.
Cache hit
A requested item is already present in the relevant cache.
Cache miss
A requested item is not present and must be obtained from another level.
Carry
A contribution passed to a more significant binary column in addition.
Carry flag
A status bit associated with carry-out or no-borrow, depending on instruction semantics.
Clock
A periodic timing signal used to coordinate state changes in synchronous logic.
Clock domain
A set of sequential components driven by a related clock signal.
Clock edge
A signal transition, commonly rising or falling, used as a sampling event.
CMOS
A common integrated-circuit technology that combines complementary types of MOS transistors.
Combinational logic
Logic whose output is a function of current inputs alone, apart from propagation delay.
Combinational loop
Feedback without registered state; requires care because it may oscillate or behave unpredictably.
Compiler
Software translating a higher-level program into another representation, often machine code.
Concurrency
Multiple activities make progress during overlapping periods.
Conditional execution
The use of a condition to decide whether an operation or branch takes effect.
Context switch
Saving one execution context and restoring another.
Control bus
The collection of control signals governing transfers or transactions.
Control ROM
A lookup table mapping control state and instruction fields to control outputs.
Control unit
Logic coordinating instruction execution by driving selectors and enable signals.
Counter
A sequential circuit whose stored number changes by a defined step.
Data bus
Signal lines transporting data values between components.
Datapath
The CPU components and connections that carry and transform data values.
Decimal
A base-ten positional number representation using the digits 0 through 9.
Decode
Interpreting instruction fields to choose an operation and its operands.
Decoder
A circuit translating a binary code into a selection or set of outputs.
Decoder output
A selected line or combination of lines asserted according to an encoded input.
Demultiplexer
A routing block that sends one input toward a selected output.
DRAM
Dynamic random-access memory storing charge, requiring periodic refresh.
Enable
A signal allowing an operation, selection or state update when asserted.
Encoder
A circuit translating active input conditions into an encoded output; behavior depends on its specification.
Endianness
The order in which bytes of a multi-byte value are arranged in addressed memory.
Exception
A special control-flow event such as a fault or deliberate system call.
Execute
Performing the operation or state transition required by an instruction.
Fan-out
The number of receiving inputs driven by one output; affects circuit loading.
Feedback
A connection where an output influences the same system again.
Fetch
Obtaining instruction bits from instruction storage or memory.
Fibonacci sequence
A sequence where each term after the first two is the sum of the previous two.
Flag
A status bit describing an operation’s outcome, such as zero or carry.
Flip-flop
A state-holding element, typically triggered by a clock edge.
Full adder
A circuit adding A, B and carry-in, producing sum and carry-out.
GPIO
General-purpose input/output pins used to exchange digital signals with external hardware.
Half adder
A circuit adding two input bits with a sum and carry output.
Hazard
A dependency or resource conflict that can disturb overlapped execution.
Hexadecimal
Base sixteen: 0–9 and A–F, with one symbol per four bits.
Hold time
Time an input must remain stable after the sampling clock edge.
Immediate
A value carried directly inside an instruction encoding.
Instruction
An encoded command whose meaning is specified by an instruction set architecture.
Instruction register
A register or pipeline state holding the instruction under interpretation.
Instruction width
The number of bits in an encoded instruction; may be fixed or variable depending on ISA.
Interrupt
A mechanism redirecting execution to handle a hardware or software event.
ISA
Instruction set architecture: the programmer-visible contract of instructions, registers and behavior.
Jump
An explicit change of the next instruction address.
Latch
A state-holding element typically controlled by an enable level.
Latency
How long an individual operation or request takes to complete.
Least significant bit
The lowest positional-weight bit, weight 1 for unsigned integers.
Load/store architecture
An architecture style in which memory access uses dedicated load/store instructions.
Logic gate
A circuit implementing a Boolean operation on one or more digital inputs.
Logic level
An interpreted state, usually LOW or HIGH, associated with a valid input range.
Machine code
Instruction encodings that can be recognized by a processor.
Memory address
A code identifying a storage location or mapped peripheral location.
Metastability
A temporary unresolved state possible when sampling asynchronous or badly timed signals.
Microarchitecture
The internal circuit organization implementing an ISA.
Microcode
Control information describing lower-level steps for implementing machine instructions.
Microstep
A smaller internal control phase used to implement one architectural instruction.
MMIO
Memory-mapped input/output: device control registers accessed through an address space.
Modulo
The remainder after division; n-bit arithmetic effectively wraps modulo 2ⁿ.
Most significant bit
The highest positional-weight bit in the chosen width.
Multiplexer
A selector that forwards one of several data inputs based on control inputs.
NAND
The inverse of AND. A universal gate for constructing Boolean functions.
Negation
Computing the additive inverse of a number; for two’s complement, invert bits and add one modulo 2ⁿ.
Negative flag
A status bit often reflecting the result’s most significant bit.
Nibble
Four bits; exactly one hexadecimal digit.
Noise margin
The allowed difference between a valid output level and the threshold that a receiver must recognize.
NOR
The inverse of OR. A universal gate for constructing Boolean functions.
NOT
A Boolean operation that inverts its single input.
Opcode
The instruction field indicating which operation is requested.
Operand
A value, register, address or encoded field used by an instruction.
OR
A Boolean operation that returns one when at least one input is one.
OS
Operating system: software coordinating hardware, programs, resources and protections.
Overflow
A condition where a mathematical result falls outside the supported range of a representation.
Parallelism
Multiple activities execute simultaneously on distinct execution resources.
PC
Abbreviation for program counter, not personal computer in this context.
Peripheral
A component outside the processor’s arithmetic core, such as a GPIO controller or timer.
Pipeline
A CPU structure overlapping stages of multiple in-flight instructions.
Process
An operating-system abstraction for a running program and its execution resources.
Program counter
State identifying the address of the next instruction fetch under the architecture’s rules.
Program trace
A step-by-step record of executed instructions and state changes.
Propagation delay
The finite time between an input change and the resulting output change.
Radix
The number base, such as two for binary or ten for decimal.
RAM
Random-access memory: locations that can be individually accessed for reading and usually writing.
Register
A small group of state elements holding a multi-bit value.
Register file
A collection of processor registers accessed through selection logic.
Register width
The number of bits held or processed by a particular register.
Reset
A control operation initializing state to a defined condition.
Ripple carry
An adder structure where carry must propagate between sequential bit stages.
ROM
Read-only memory: a memory-like interface delivering pre-established data or lookup values.
Sampling
Capturing the value of a signal at a defined observation time.
Scheduler
The operating-system component deciding when runnable tasks receive CPU time.
Sequential logic
Logic whose behavior depends on inputs and retained state.
Setup time
Time an input must be stable before the sampling clock edge.
Seven-segment display
An arrangement of seven individually controlled segments used to show digits.
Signed integer
An interpretation permitting negative values, commonly using two’s complement.
Signed overflow
A result outside the fixed-width signed range; distinct from unsigned carry-out.
SoC
System on a chip: a chip integrating CPU cores and additional controllers or accelerators.
SRAM
Static random-access memory built from bistable storage cells; common in caches.
Thread
An execution sequence sharing a process’s resources with peer threads.
Throughput
How much work a system completes per unit time.
Transistor
A semiconductor component that can control current; the central switching device in ordinary digital circuits.
Tri-state output
A digital output that may drive low, drive high, or electrically disconnect, depending on design.
Truth table
A complete listing of input combinations and corresponding outputs for a logical function.
Two’s complement
A signed fixed-width representation that uses modular arithmetic and a negative leading-bit weight.
Unsigned integer
An interpretation where all bit-position weights are nonnegative.
Virtual memory
An address-space abstraction mapped to physical storage under system rules.
Voltage
An electrical potential difference. Logic circuits interpret ranges of voltages as low or high.
Word
A group of bits of implementation- or architecture-defined size.
Writeback
A stage that commits a computed result to an architectural destination in many CPU descriptions.
XNOR
Exclusive NOR: one if the two inputs match.
XOR
Exclusive OR: one if the two inputs differ.
Zero flag
A status bit indicating that the relevant operation produced zero.